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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
TABLE 24-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)  
Param.  
No.  
Symbol  
Characteristic  
100 kHz mode  
Min  
Max  
Units  
Conditions  
100  
THIGH  
Clock High Time  
Clock Low Time  
4.0  
0.6  
μs  
μs  
400 kHz mode  
MSSP Module  
100 kHz mode  
400 kHz mode  
MSSP Module  
1.5 TCY  
4.7  
101  
TLOW  
μs  
μs  
1.3  
1.5 TCY  
102  
103  
TR  
SDAx and SCLx Rise Time 100 kHz mode  
400 kHz mode  
1000  
300  
ns  
ns  
20 + 0.1 CB  
CB is specified to be from  
10 to 400 pF  
TF  
SDAx and SCLx Fall Time 100 kHz mode  
400 kHz mode  
300  
300  
ns  
ns  
20 + 0.1 CB  
CB is specified to be from  
10 to 400 pF  
90  
TSU:STA  
Start Condition Setup Time 100 kHz mode  
400 kHz mode  
4.7  
0.6  
4.0  
0.6  
0
μs  
μs  
μs  
μs  
ns  
μs  
ns  
ns  
μs  
μs  
ns  
ns  
μs  
μs  
Only relevant for Repeated  
Start condition  
91  
THD:STA Start Condition Hold Time 100 kHz mode  
400 kHz mode  
After this period, the first clock  
pulse is generated  
106  
107  
92  
THD:DAT Data Input Hold Time  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
0
0.9  
TSU:DAT Data Input Setup Time  
250  
100  
4.7  
0.6  
(Note 2)  
TSU:STO Stop Condition Setup Time 100 kHz mode  
400 kHz mode  
109  
110  
TAA  
Output Valid from Clock  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
3500  
(Note 1)  
TBUF  
Bus Free Time  
4.7  
1.3  
Time the bus must be free  
before a new transmission can  
start  
D102  
CB  
Bus Capacitive Loading  
400  
pF  
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)  
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.  
2
2
2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT 250 ns,  
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.  
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,  
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCLx  
line is released.  
DS39682E-page 330  
© 2009 Microchip Technology Inc.  
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