PIC18FXX20
FIGURE 26-18:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
83
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
bit6 - - - - - -1
bit6 - - - -1
77
75, 76
MSb In
74
LSb In
73
Note:
Refer to Figure 26-6 for load conditions.
TABLE 26-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
—
ns
71
71A
72
72A
73
TscH
SCK input high time
(Slave mode)
SCK input low time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
ns
ns
ns
ns
40
1.25 TCY + 30
40
(Note 1)
(Note 1)
TscL
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
73A
74
TB2B
Last clock edge of Byte1 to the first clock edge of Byte2
1.5 TCY + 40
100
—
—
ns
ns
(Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
75
TdoR
TdoF
SDO data output rise time
SDO data output fall time
PIC18FXX20
PIC18LFXX20
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
—
10
—
TssH2doZ SS ↑ to SDO output hi-impedance
TscR
SCK output rise time (Master mode)
PIC18FXX20
PIC18LFXX20
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after SCK edge PIC18FXX20
TscL2doV
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
PIC18LFXX20
83
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39609A-page 332
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
