PIC18FXX20
FIGURE 23-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
(2)
TOST
INTF flag
Interrupt Latency(3)
(INTCON<1>)
GIEH bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+2
PC+4
PC+4
PC + 4
0008h
000Ah
Instruction
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(000Ah)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Inst(PC + 2)
Dummy Cycle
Dummy Cycle
Inst(0008h)
SLEEP
Inst(PC - 1)
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.
4: CLKO is not available in these Osc modes, but shown here for timing reference.
In the PIC18FXX20 family, the block size varies with
23.4 Program Verification and
the size of the user program memory. For PIC18FX520
Code Protection
devices, program memory is divided into four blocks of
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro devices. The user program memory is
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
• Code Protect bit (CPn)
• Write Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices, and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CONFIG5H
CONFIG6L WRT7*
CONFIG6H WRTD
CONFIG7L EBTR7* EBTR6* EBTR5* EBTR4*
CONFIG7H EBTRB
CP7*
CPD
CP6*
CPB
WRT6*
WRTB
CP5*
—
WRT5*
WRTC
CP4*
—
WRT4*
—
CP3
—
WRT3
—
EBTR3
—
CP2
—
WRT2
—
EBTR2
—
CP1
—
WRT1
—
EBTR1
—
CP0
—
WRT0
—
EBTR0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
—
—
Legend: Shaded cells are unimplemented.
* Unimplemented in PIC18FX520 and PIC18FX620 devices.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 253
MICROCHIP [ MICROCHIP ]
