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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
External MCLR Reset will cause a device RESET. All  
other events are considered a continuation of program  
execution and will cause a “wake-up”. The TO and PD  
bits in the RCON register can be used to determine the  
cause of the device RESET. The PD bit, which is set on  
power-up, is cleared when SLEEP is invoked. The TO  
bit is cleared if a WDT time-out occurred (and caused  
wake-up).  
When the SLEEPinstruction is being executed, the next  
instruction (PC + 2) is pre-fetched. For the device to  
wake-up through an interrupt event, the corresponding  
interrupt enable bit must be set (enabled). Wake-up is  
regardless of the state of the GIE bit. If the GIE bit is  
clear (disabled), the device continues execution at the  
instruction after the SLEEPinstruction. If the GIE bit is  
set (enabled), the device executes the instruction after  
the SLEEP instruction and then branches to the inter-  
rupt address. In cases where the execution of the  
instruction following SLEEP is not desirable, the user  
should have a NOPafter the SLEEPinstruction.  
23.3 Power-down Mode (SLEEP)  
Power-down mode is entered by executing a SLEEP  
instruction.  
If enabled, the Watchdog Timer will be cleared, but  
keeps running, the PD bit (RCON<3>) is cleared, the  
TO (RCON<4>) bit is set, and the oscillator driver is  
turned off. The I/O ports maintain the status they had  
before the SLEEP instruction was executed (driving  
high, low, or hi-impedance).  
For lowest current consumption in this mode, place all  
I/O pins at either VDD or VSS, ensure no external cir-  
cuitry is drawing current from the I/O pin, power-down  
the A/D and disable external clocks. Pull all I/O pins  
that are hi-impedance inputs, high or low externally, to  
avoid switching currents caused by floating inputs. The  
T0CKI input should also be at VDD or VSS for lowest  
current consumption. The contribution from on-chip  
pull-ups on PORTB should be considered.  
The MCLR pin must be at a logic high level (VIHMC).  
23.3.2  
WAKE-UP USING INTERRUPTS  
23.3.1  
WAKE-UP FROM SLEEP  
When global interrupts are disabled (GIE cleared) and  
any interrupt source has both its interrupt enable bit  
and interrupt flag bit set, one of the following will occur:  
• If an interrupt condition (interrupt flag bit and inter-  
rupt enable bits are set) occurs before the execu-  
tion of a SLEEPinstruction, the SLEEPinstruction  
will complete as a NOP. Therefore, the WDT and  
WDT postscaler will not be cleared, the TO bit will  
not be set and PD bits will not be cleared.  
• If the interrupt condition occurs during or after  
the execution of a SLEEPinstruction, the device  
will immediately wake-up from SLEEP. The  
SLEEPinstruction will be completely executed  
before the wake-up. Therefore, the WDT and  
WDT postscaler will be cleared, the TO bit will be  
set and the PD bit will be cleared.  
Even if the flag bits were checked before executing a  
SLEEP instruction, it may be possible for flag bits to  
become set before the SLEEPinstruction completes. To  
determine whether a SLEEPinstruction executed, test  
the PD bit. If the PD bit is set, the SLEEP instruction  
was executed as a NOP.  
The device can wake-up from SLEEP through one of  
the following events:  
1. External RESET input on MCLR pin.  
2. Watchdog Timer Wake-up (if WDT was  
enabled).  
3. Interrupt from INT pin, RB port change or a  
peripheral interrupt.  
The following peripheral interrupts can wake the device  
from SLEEP:  
1. PSP read or write.  
2. TMR1 interrupt. Timer1 must be operating as an  
asynchronous counter.  
3. TMR3 interrupt. Timer3 must be operating as an  
asynchronous counter.  
4. CCP Capture mode interrupt.  
5. Special event trigger (Timer1 in Asynchronous  
mode using an external clock).  
6. MSSP (START/STOP) bit detect interrupt.  
7. MSSP transmit or receive in Slave mode  
(SPI/I2C).  
8. USART RX or TX (Synchronous Slave mode).  
9. A/D conversion (when A/D clock source is RC).  
10. EEPROM write operation complete.  
11. LVD interrupt.  
To ensure that the WDT is cleared, a CLRWDTinstruction  
should be executed before a SLEEPinstruction.  
Other peripherals cannot generate interrupts, since  
during SLEEP, no on-chip clocks are present.  
DS39609A-page 252  
Advance Information  
2003 Microchip Technology Inc.  
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