PIC18FXX20
17.3.8
SLEEP OPERATION
17.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to
transmit/receive data.
Table 17-1 shows the compatibility between the
standard SPI modes and the states the CKP and CKE
control bits.
TABLE 17-1: SPI BUS MODES
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
17.3.9
EFFECTS OF A RESET
There is also a SMP bit, which controls when the data
is sampled.
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
POR,
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
1111 1111 1111 1111
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON
PORTC Data Direction Register
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3
Synchronous Serial Port Receive Buffer/Transmit Register
TRISF2
TRISF1 TRISF0 1111 1111 uuuu uuuu
xxxx xxxx uuuu uuuu
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1 SSPM0 0000 0000 0000 0000
SSPSTAT
UA
BF
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 165
MICROCHIP [ MICROCHIP ]
