PIC18CXX2
Register 7-3: INTCON3 Register
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
INT2IF
R/W-0
INT1IF
—
—
INT2IP
INT1IP
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1=High priority
0=Low priority
INT1IP: INT1 External Interrupt Priority bit
1=High priority
0=Low priority
bit 5
bit 4
Unimplemented: Read as '0'
INT2IE: INT2 External Interrupt Enable bit
1=Enables the INT2 external interrupt
0=Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1=Enables the INT1 external interrupt
0=Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as '0'
INT2IF: INT2 External Interrupt Flag bit
1=The INT2 external interrupt occurred
(must be cleared in software)
0=The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1=The INT1 external interrupt occurred
(must be cleared in software)
0=The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 69
MICROCHIP [ MICROCHIP ]
