PIC18CXX2
TMR1L Register ................................................. 97, 105
Timer2
Receive Block Diagram ................................... 159
Reception ........................................................ 160
Transmit Block Diagram .................................. 157
Baud Rate Generator (BRG) ................................... 153
Baud Rate Error, Calculating ........................... 153
Baud Rate Formula ......................................... 153
Baud Rates, Asynchronous Mode (BRGH=0) . 155
Baud Rates, Asynchronous Mode (BRGH=1) . 156
Baud Rates, Synchronous Mode ..................... 154
High Baud Rate Select (BRGH Bit) ................. 153
Sampling ......................................................... 153
Serial Port Enable (SPEN Bit) ................................. 151
Synchronous Master Mode ...................................... 161
Reception ........................................................ 164
Timing Diagram, Synchronous Receive .......... 269
Timing Diagram, Synchronous Transmission .. 268
Transmission ................................................... 162
Synchronous Slave Mode ........................................ 165
Block Diagram .......................................................... 103
Postscaler. See Postscaler, Timer2
PR2 Register .................................................... 102, 115
Prescaler. See Prescaler, Timer2
SSP Clock Shift ................................................ 102, 103
TMR2 Register ......................................................... 102
TMR2 to PR2 Match Interrupt .................. 102, 103, 115
Timing Diagrams
Acknowledge Sequence Timing ............................... 142
Baud Rate Generator with Clock Arbitration ............ 136
BRG Reset Due to SDA Collision ............................ 147
Bus Collision
Start Condition Timing ..................................... 146
Bus Collision During a Restart Condition (Case 1) .. 148
Bus Collision During a Restart Condition (Case2) ... 148
Bus Collision During a Start Condition (SCL = 0) .... 147
Bus Collision During a Stop Condition ..................... 149
Bus Collision for Transmit and Acknowledge ........... 145
W
2
Wake-up from SLEEP .............................................. 181, 187
Timing Diagram ....................................................... 188
Watchdog Timer (WDT) ........................................... 181, 185
Block Diagram ......................................................... 186
Programming Considerations .................................. 185
RC Oscillator ........................................................... 185
Time-out Period ....................................................... 185
Timing Diagram ....................................................... 256
Waveform for General Call Address Sequence ............... 133
WCOL .............................................................. 137, 139, 142
WCOL Status Flag ........................................................... 137
WWW, On-Line Support ...................................................... 4
I C Bus Data ............................................................ 267
2
I C Master Mode First Start bit timing ...................... 137
2
I C Master Mode Reception timing .......................... 141
2
I C Master Mode Transmission timing ..................... 140
Master Mode Transmit Clock Arbitration .................. 144
Repeat Start Condition ............................................. 138
Slave Synchronization ............................................. 125
SPI Mode Timing (Master Mode)SPI Mode
Master Mode Timing Diagram ......................... 124
SPI Mode Timing (Slave Mode with CKE = 0) ......... 126
SPI Mode Timing (Slave Mode with CKE = 1) ......... 126
Stop Condition Receive or Transmit ........................ 143
Time-out Sequence on Power-up ........................ 30, 31
USART Asynchronous Master Transmission ........... 158
USART Asynchronous Reception ............................ 160
USART Synchronous Reception .............................. 164
USART Synchronous Transmission ........................ 162
Wake-up from SLEEP via Interrupt .......................... 188
Timing Diagrams and Specifications ................................ 253
A/D Conversion ........................................................ 271
Brown-out Reset (BOR) ........................................... 256
Capture/Compare/PWM (CCP) ................................ 258
CLKOUT and I/O ...................................................... 255
External Clock .......................................................... 253
X
XORLW ........................................................................... 233
XORWF ........................................................................... 234
Z
Z ........................................................................................ 54
2
I C Bus Data ............................................................ 265
2
I C Bus Start/Stop Bits ............................................. 264
Oscillator Start-up Timer (OST) ............................... 256
Parallel Slave Port (PSP) ......................................... 259
Power-up Timer (PWRT) ......................................... 256
Reset ........................................................................ 256
Timer0 and Timer1 ................................................... 257
USART Synchronous Receive ( Master/Slave) ....... 269
USART SynchronousTransmission ( Master/Slave) 268
Watchdog Timer (WDT) ........................................... 256
TRISE Register .................................................................. 87
PSPMODE Bit ...................................................... 85, 90
TSTFSZ ........................................................................... 233
TXSTA Register
BRGH Bit ................................................................. 153
U
Universal Synchronous Asynchronous Receiver Transmitter.
See USART
USART ............................................................................. 151
Asynchronous Mode ................................................ 157
Master Transmission ....................................... 158
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 291
MICROCHIP [ MICROCHIP ]
