PIC18CXX2
14.3.12 CLOCK ARBITRATION
14.3.13 SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated start/stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 14-22).
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor from
sleep (if the MSSP interrupt is enabled).
14.3.14 EFFECT OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
FIGURE 14-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
to measure high time interval
SCL = 1 BRG starts counting
clock high interval.
SCL
SDA
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
TBRG
TBRG
TBRG
DS39026B-page 144
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
