PIC18CXX2
14.3.5 BAUD RATE GENERATOR
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
In I2C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 14-14: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKOUT
Fosc/4
FIGURE 14-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count.
BRG
reload
DS39026B-page 136
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
