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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
SUBWFB  
Syntax:  
Subtract W from f with Borrow  
SWAPF  
Swap f  
Syntax:  
[ label ] SWAPF f [,d [,a]]  
[ label ] SUBWFB f [,d [,a]]  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operation:  
(f<3:0>) dest<7:4>,  
(f<7:4>) dest<3:0>  
Operation:  
(f) – (W) – (C) dest  
Status Affected:  
Encoding:  
N, OV, C, DC, Z  
Status Affected:  
Encoding:  
None  
0101  
10da  
ffff  
ffff  
0011  
10da  
ffff  
ffff  
Description:  
Subtract W and the Carry flag (borrow)  
from register, ‘f’ (2’s complement  
Description:  
The upper and lower nibbles of register,  
‘f’, are exchanged. If ‘d’ is ‘0’, the result  
is placed in W. If ‘d’ is ‘1’, the result is  
placed in register, ‘f’. If ‘a’ is ‘0’, the  
Access Bank will be selected, overrid-  
ing the BSR value. If ‘a’ is ‘1’, then the  
bank will be selected as per the BSR  
value.  
method). If ‘d’ is ‘0’, the result is stored in  
W. If ‘d’ is ‘1’, the result is stored back in  
register, ‘f’. If ‘a’ is ‘0’, the Access Bank  
will be selected, overriding the BSR  
value. If ‘a’ is ‘1’, then the bank will be  
selected as per the BSR value.  
Words:  
Cycles:  
1
1
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Q2  
Q3  
Q4  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
destination  
Example 1:  
SUBWFB REG, 1, 0  
Before Instruction  
Example:  
SWAPF  
REG  
REG  
W
C
=
=
=
0x19  
0x0D  
0x01  
(0001 1001)  
(0000 1101)  
Before Instruction  
REG  
=
0x53  
0x35  
After Instruction  
After Instruction  
REG  
=
REG  
W
C
Z
N
=
0x0C  
0x0D  
0x01  
0x00  
0x00  
(0000 1011)  
(0000 1101)  
=
=
=
=
; result is positive  
Example 2:  
SUBWFB REG, 0, 0  
Before Instruction  
REG  
W
C
=
=
=
0x1B  
0x1A  
0x00  
(0001 1011)  
(0001 1010)  
(0001 1011)  
; result is zero  
After Instruction  
REG  
W
C
Z
N
=
0x1B  
0x00  
0x01  
0x01  
0x00  
=
=
=
=
Example 3:  
Before Instruction  
SUBWFB REG, 1, 0  
REG  
W
C
=
=
=
0x03  
0x0E  
0x01  
(0000 0011)  
(0000 1101)  
After Instruction  
REG  
=
0xF5  
(1111 0100)  
; [2’s comp]  
W
C
Z
=
=
=
=
0x0E  
0x00  
0x00  
0x01  
(0000 1101)  
N
; result is negative  
DS39616D-page 320  
2010 Microchip Technology Inc.  
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