PIC18F2331/2431/4331/4431
21.2 A/D Result Buffer
21.3 A/D Acquisition Requirements
The A/D module has a 4-level result buffer with an
address range of 0 to 3, enabled by setting the FIFOEN
bit in the ADCON1 register. This buffer is implemented
in a circular fashion, where the A/D result is stored in
one location and the address is incremented. If the
address is greater than 3, the pointer is wrapped back
around to 0. The result buffer has a Buffer Empty Flag,
BFEMT, indicating when any data is in the buffer. It also
has a Buffer Overflow Flag, BFOVFL, which indicates
when a new sample has overwritten a location that was
not previously read.
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 21-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Associated with the buffer is a pointer to the address for
the next read operation. The ADPNT<1:0> bits
configure the address for the next read operation.
These bits are read-only.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
The Result Buffer also has a configurable interrupt
trigger level that is configured by the ADRS<1:0> bits.
The user has three selections: interrupt flag set on
every write to the buffer, interrupt on every second write
to the buffer, or interrupt on every fourth write to the
buffer. ADPNT<1:0> are reset to ‘00’ every time a
conversion sequence is started (either by setting the
GO/DONE bit or on a trigger).
To calculate the minimum acquisition time,
Equation 21-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Note:
When right justified, reading ADRESL
increments the ADPNT<1:0> bits. When
left justified, reading ADRESH increments
the ADPNT<1:0> bits.
Example 21-1 shows the calculation of the minimum
required acquisition time TACQ. In this case, the
converter module is fully powered up at the outset and
therefore, the amplifier settling time, TAMP, is negligible.
This calculation is based on the following application
system assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
=
=
=
9 pF
100
1/2 LSb
5V Rss = 6 k
50°C (system max.)
0V @ time = 0
EQUATION 21-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 21-2: MINIMUM A/D HOLDING CAPACITOR CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
2010 Microchip Technology Inc.
DS39616D-page 249
MICROCHIP [ MICROCHIP ]
