PIC18F2331/2431/4331/4431
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When triggered, the A/D module continues to sample
the input for the selected acquisition time, then
21.4 A/D Voltage References
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source
impedance of the VREF+ and VREF- voltage sources
must be considered. During acquisition, currents
supplied by these sources are insignificant. However,
during conversion, the A/D module sinks and sources
current through the reference sources.
automatically begins
a
conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and triggering the A/D. If an acquisition time is
programmed, there is nothing to indicate if the
acquisition time has ended or if the conversion has
begun.
In order to maintain the A/D accuracy, the voltage
reference source impedances should be kept low to
reduce voltage changes. These voltage changes occur
as reference currents flow through the reference
source impedance.
21.6 Selecting the A/D Conversion
Clock
Note:
When using external references, the
source impedance of the external voltage
references must be less than 75 in order
to achieve the specified ADC resolution. A
higher reference source impedance will
increase the ADC offset and gain errors.
Resistive voltage dividers will not provide a
low enough source impedance. To ensure
the best possible ADC performance, exter-
nal VREF inputs should be buffered with an
op amp or other low-impedance circuit.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are eight possible options for TAD:
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
• Internal RC Oscillator/4
21.5 Selecting and Configuring
Automatic Acquisition Time
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (approximately 416 ns, see parameter
A11 for more information).
The ADCON2 register allows the user to select an acqui-
sition time that occurs each time an A/D conversion is
triggered.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring
the required acquisition time has passed between
selecting the desired input channel and the start of
conversion. This occurs when the ACQT<3:0> bits
(ADCON2<6:3>) remain in their Reset state (‘0000’).
Table 21-2 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 21-2: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS<2:0>
PIC18FXX31
PIC18LFXX31(4)
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC/4(3)
RC(3)
000
100
001
101
010
110
011
111
4.8 MHz
9.6 MHz
666 kHz
1.33 MHz
2.66 MHz
5.33 MHz
10.65 MHz
21.33 MHz
1.00 MHz(2)
4.0 MHz(2)
19.2 MHz
38.4 MHz
40.0 MHz
40.0 MHz
1.00 MHz(1)
4.0 MHz(2)
Note 1: The RC source has a typical TAD time of 2-6 s.
2: The RC source has a typical TAD time of 0.5-1.5 s.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification unless in Single-Shot mode.
4: Low-power devices only.
2010 Microchip Technology Inc.
DS39616D-page 251
MICROCHIP [ MICROCHIP ]
