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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
Clearing the GO/DONE bit during a conversion will  
abort the current conversion. The resulting buffer loca-  
tion will contain the partially completed A/D conversion  
sample. This will not set the ADIF flag, therefore, the  
user must read the buffer location before a conversion  
sequence overwrites it.  
21.9 A/D Conversions  
Figure 21-3 shows the operation of the A/D Converter  
after the GO/DONE bit has been set and the  
ACQT<2:0> bits are cleared. A conversion is started  
after the following instruction to allow entry into Sleep  
mode before the conversion begins. The internal A/D  
RC oscillator must be selected to perform a conversion  
in Sleep.  
After the A/D conversion is completed or aborted, a  
2 TAD wait is required before the next acquisition can be  
started. After this wait, acquisition on the selected  
channel is automatically started.  
Figure 21-4 shows the operation of the A/D Converter  
after the GO/DONE bit has been set, the ACQT<3:0>  
bits are set to ‘010’ and a 4 TAD acquisition time is  
selected before the conversion starts.  
Note: The GO/DONE bit should NOT be set in  
the same instruction that turns on the A/D.  
FIGURE 21-3:  
GO/DONE bit is  
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)  
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11  
b6  
set and holding  
cap is  
b8  
b4  
b3  
b2  
b9  
b5  
b7  
b0  
b1  
disconnected  
from analog  
input  
Conversion Starts  
GO/DONE bit cleared on the rising edge of Q1 after the first Q3  
following TAD11 and result buffer is loaded.(1)  
Note 1: Conversion time is a minimum of 11 TAD + 2 TCY and a maximum of 11 TAD + 6 TCY.  
FIGURE 21-4:  
A/D CONVERSION TAD CYCLES (ACQT<3:0> = 0010, TACQ = 4 TAD)  
TACQT Cycles  
TAD Cycles  
1
2
3
4
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11  
b6  
b9  
Conversion Starts  
(Holding capacitor is disconnected)  
b8  
b5  
b4  
b3  
b2  
b7  
b0  
b1  
Automatic  
Acquisition  
Time  
A/D Triggered  
GO/DONE bit cleared on the rising edge of Q1 after the first Q3  
following TAD11 and result buffer is loaded.(1)  
Note 1: In Continuous modes, next conversion starts at the end of TAD12.  
2010 Microchip Technology Inc.  
DS39616D-page 253  
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