欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4431-I/P的Datasheet PDF文件第242页浏览型号PIC18F4431-I/P的Datasheet PDF文件第243页浏览型号PIC18F4431-I/P的Datasheet PDF文件第244页浏览型号PIC18F4431-I/P的Datasheet PDF文件第245页浏览型号PIC18F4431-I/P的Datasheet PDF文件第247页浏览型号PIC18F4431-I/P的Datasheet PDF文件第248页浏览型号PIC18F4431-I/P的Datasheet PDF文件第249页浏览型号PIC18F4431-I/P的Datasheet PDF文件第250页  
PIC18F2331/2431/4331/4431  
The A/D channels are grouped into four sets of 2 or  
3 channels. For the PIC18F2331/2431 devices, AN0  
and AN4 are in Group A, AN1 is in Group B, AN2 is in  
Group C and AN3 is in Group D. For the PIC18F4331/  
4431 devices, AN0, AN4 and AN8 are in Group A, AN1  
and AN5 are in Group B, AN2 and AN6 are in Group C  
and AN3 and AN7 are in Group D. The selected chan-  
nel in each group is selected by configuring the A/D  
Channel Select Register, ADCHS.  
The A/D Converter has a unique feature of being able  
to operate while the device is in Sleep mode. To  
operate in Sleep, the A/D conversion clock must be  
derived from the A/D’s internal RC oscillator.  
A device Reset forces all registers to their Reset state.  
This forces the A/D module to be turned off and any  
conversion in progress is aborted.  
Each port pin associated with the A/D Converter can  
individually be configured as an analog input or digital  
I/O using the ANSEL0 and ANSEL1 registers. The  
ADRESH and ADRESL registers contain the value in  
the result buffer pointed to by ADPNT<1:0>  
(ADCON1<1:0>). The result buffer is a 4-deep circular  
buffer that has a Buffer Empty status bit, BFEMT  
(ADCON1<3>), and a Buffer Overflow status bit,  
BFOVFL (ADCON1<2>).  
The analog voltage reference is software selectable to  
either the device’s positive and negative analog supply  
voltage (AVDD and AVSS), or the voltage level on the  
RA3/AN3/VREF+/CAP2/QEA and RA2/AN2/VREF-/  
CAP1/INDX, or some combination of supply and  
external sources. Register ADCON1 controls the  
voltage reference settings.  
FIGURE 21-1:  
A/D BLOCK DIAGRAM  
VCFG<1:0>  
(2)  
(2)  
AVSS  
AVDD  
VREF+  
VREF-  
VREFH  
VREFL  
ADC  
AN0  
AN4  
AN8(1)  
Analog  
MUX  
ADRESH, ADRESL  
MUX  
10  
AN2/VREF-  
ADPNT<1:0>  
AN6(1)  
00  
01  
10  
11  
1
2
3
4
S/H-1  
+
ACMOD<1:0>,  
GxSEL<1:0>  
S/H  
-
4x10-Bit FIFO  
AVSS  
ACONV  
ACSCH  
ACMODx  
AN1  
AN5(1)  
Analog  
MUX  
AN3/VREF+  
S/H-2  
+
AN7(1)  
S/H  
-
(2)  
ACMOD<1:0>,  
GxSEL<1:0>  
AVSS  
Seq.  
Cntrl.  
Note 1: AN5 through AN8 are available only on PIC18F4331/4431 devices.  
2: I/O pins have diode protection to VDD and VSS.  
DS39616D-page 246  
2010 Microchip Technology Inc.  
 复制成功!