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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
An SSP interrupt is generated for each data transfer  
byte. Flag bit, SSPIF, must be cleared in software and  
the SSPSTAT register is used to determine the status  
of the byte. Flag bit, SSPIF, is set on the falling edge of  
the ninth clock pulse.  
19.3.1.3  
Transmission  
When the R/W bit of the incoming address byte is set  
and an address match occurs, the R/W bit of the  
SSPSTAT register is set. The received address is  
loaded into the SSPBUF register. The ACK pulse will  
be sent on the ninth bit and pin, SCK/SCL, is held low.  
The transmit data must be loaded into the SSPBUF  
register, which also loads the SSPSR register. Then,  
pin, SCK/SCL, should be enabled by setting bit, CKP  
(SSPCON<4>). The master must monitor the SCL pin  
prior to asserting another clock pulse. The slave  
devices may be holding off the master by stretching the  
clock. The eight data bits are shifted out on the falling  
edge of the SCL input. This ensures that the SDA signal  
is valid during the SCL high time (Figure 19-7).  
As a slave-transmitter, the ACK pulse from the master-  
receiver is latched on the rising edge of the ninth SCL  
input pulse. If the SDA line was high (not ACK), then the  
data transfer is complete. When the ACK is latched by  
the slave, the slave logic is reset and the slave then  
monitors for another occurrence of the Start bit. If the  
SDA line was low (ACK), the transmit data must be  
loaded into the SSPBUF register, which also loads the  
SSPSR register. Then pin, SCK/SCL, should be enabled  
by setting bit CKP.  
FIGURE 19-7:  
I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)  
Receiving Address  
R/W = 1  
ACK  
Transmitting Data  
ACK  
9
SDA  
A7 A6 A5 A4 A3 A2 A1  
D7 D6 D5 D4 D3 D2 D1 D0  
SCL  
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
SCL held low  
while CPU  
responds to SSPIF  
Data in  
sampled  
Cleared in software  
SSPIF (PIR1<3>)  
BF (SSPSTAT<0>)  
CKP (SSPCON<4>)  
From SSP Interrupt  
Service Routine  
SSPBUF is written in software  
Set bit after writing to SSPBUF  
(SSPBUF must be written to  
before the CKP bit can be set)  
2010 Microchip Technology Inc.  
DS39616D-page 215