PIC18F2331/2431/4331/4431
FIGURE 19-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 1
bit 0
SDI (SMP = 0)
bit 0
bit 7
SSPIF
TABLE 19-1: REGISTERS ASSOCIATED WITH SPI OPERATION
ResetValues
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INT0IF
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
TMR0IF
RBIF
54
57
57
57
55
55
57
55
—
—
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
PIE1
TRISC
PORTC Data Direction Register
SSPBUF SSP Receive Buffer/Transmit Register
SSPCON
TRISA
WCOL
SSPOV
SSPEN
CKP
SSPM3 SSPM2
SSPM1
UA
SSPM0
BF
TRISA7(1) TRISA6(2) PORTA Data Direction Register
SSPSTAT
SMP CKE D/A
P
S
R/W
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
Note 1: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other
oscillator modes.
2: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6)
Oscillator modes only and read ‘0’ in all other oscillator modes.
2010 Microchip Technology Inc.
DS39616D-page 211
MICROCHIP [ MICROCHIP ]
