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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
TABLE 11-9: PORTE I/O SUMMARY  
TRIS  
Setting  
I/O  
Pin  
RE0/AN6  
Function  
I/O  
Description  
Type  
RE0  
0
1
1
0
1
1
0
1
1
O
I
DIG  
ST  
LATE<0> data output; not affected by analog input.  
PORTE<0> data input; disabled when analog input is enabled.  
A/D Input Channel 6. Default input configuration on POR.  
LATE<1> data output; not affected by analog input.  
AN6  
RE1  
I
ANA  
DIG  
ST  
RE1/AN7  
O
I
PORTE<1> data input; disabled when analog input is enabled.  
A/D Input Channel 7. Default input configuration on POR.  
LATE<2> data output; not affected by analog input.  
AN7  
RE2  
I
ANA  
DIG  
ST  
RE2/AN8  
O
I
PORTE<2> data input; disabled when analog input is enabled.  
A/D Input Channel 8. Default input configuration on POR.  
AN8  
I
ANA  
ST  
(1)  
MCLR/VPP/RE3  
MCLR  
I
External Master Clear input; enabled when MCLRE Configuration bit  
is set.  
VPP  
I
I
ANA  
ST  
High-Voltage Detection; used for ICSP™ mode entry detection. Always  
available, regardless of pin mode.  
(2)  
RE3  
PORTE<3> data input; enabled when MCLRE Configuration bit is  
clear.  
Legend:  
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;  
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).  
Note 1: All PORTE pins are only implemented on 40/44-pin devices.  
2: RE3 does not have a corresponding TRIS bit to control data direction.  
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE  
Reset Values  
on Page:  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
PORTE  
RE3(1)  
RE2  
RE1  
RE0  
57  
57  
57  
56  
56  
LATE  
LATE Data Output Register  
PORTE Data Direction Register  
TRISE  
ANSEL0  
ANSEL1  
ANS7(2) ANS6(2) ANS5(2)  
ANS4  
ANS3  
ANS2  
ANS1  
ANS0  
ANS8(2)  
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.  
Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). It is available for  
PIC18F4331/4431 devices only.  
2: ANS5 through ANS8 are available only on PIC18F4331/4431 devices.  
2010 Microchip Technology Inc.  
DS39616D-page 125  
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