PIC18FXX20
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
2.4
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is a maximum
1.5 µs start-up required after a Power-on Reset, or
wake-up from SLEEP mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
(ECIOCONFIGURATION)
OSC1
PIC18FXX20
I/O (OSC2)
Clock from
Ext. System
RA6
2.5
HS/PLL
A Phase Locked Loop circuit (PLL) is provided as a
programmable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
OSC1
PIC18FXX20
OSC2
Clock from
Ext. System
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The Oscillator mode is specified during
device programming.
FOSC/4
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1. Also, PLL operation cannot be changed
“on-the-fly”. To enable or disable it, the controller must
either cycle through a Power-on Reset, or switch the
clock source from the main oscillator to the Timer1
oscillator and back again. (See Section 2.6 for details
on Oscillator Switching.)
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6:
PLL BLOCK DIAGRAM
(from Configuration
bit Register)
HS Osc
PLL Enable
Phase
OSC2
OSC1
Comparator
FIN
FOUT
Loop
Filter
VCO
Crystal
Osc
SYSCLK
Divide by 4
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 23
MICROCHIP [ MICROCHIP ]
