PIC18FXX20
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Pin Name
Description
Type
PIC18F6X20 PIC18F8X20
PORTJ is a bi-directional I/O port(5)
.
RJ0/ALE
RJ0
—
—
—
—
—
—
—
—
62
61
60
59
39
40
41
42
I/O
O
ST
Digital I/O.
ALE
TTL
External memory Address Latch Enable.
RJ1/OE
RJ1
I/O
O
ST
TTL
Digital I/O.
External memory Output Enable.
OE
RJ2/WRL
RJ2
I/O
O
ST
TTL
Digital I/O.
External memory Write Low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
TTL
Digital I/O.
External memory Write High control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
TTL
Digital I/O.
External memory Byte Address 0 control.
BA0
RJ5/CE
RJ5
I/O
O
ST
TTL
Digital I/O.
External memory Chip Enable control.
CE
RJ6/LB
RJ6
I/O
O
ST
TTL
Digital I/O.
External memory Low Byte select.
LB
RJ7/UB
RJ7
I/O
O
ST
TTL
Digital I/O.
External memory High Byte select.
UB
VSS
9, 25,
11, 31,
51, 70
12, 32,
48, 71
26
25
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
41, 56
VDD
10, 26,
38, 57
20
19
P
(6)
AVSS
AVDD
P
P
—
—
Ground reference for analog modules.
Positive supply for analog modules.
(6)
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
= Power
O
= Output
= Open Drain (no P diode to VDD)
P
OD
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper
operation of the part in User or ICSP modes. See parameter D001A for details.
DS39609A-page 20
AdvanceInformation
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
