欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F2320-I/SP的Datasheet PDF文件第71页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第72页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第73页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第74页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第76页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第77页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第78页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第79页  
PIC18F2220/2320/4220/4320  
REGISTER 6-1:  
EECON1 REGISTER  
R/W-x  
R/W-x  
CFGS  
U-0  
R/W-0  
FREE  
R/W-x  
R/W-0  
WREN  
R/S-0  
WR  
R/S-0  
RD  
EEPGD  
WRERR  
bit 7  
bit 0  
bit 7  
bit 6  
EEPGD: Flash Program or Data EEPROM Memory Select bit  
1= Access program Flash memory  
0= Access data EEPROM memory  
CFGS: Flash Program/Data EE or Configuration Select bit  
1= Access configuration registers  
0= Access program Flash or data EEPROM memory  
bit 5  
bit 4  
Unimplemented: Read as ‘0’  
FREE: Flash Row Erase Enable bit  
1= Erase the program memory row addressed by TBLPTR on the next WR command  
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)  
0= Perform write only  
bit 3  
WRERR: EEPROM Error Flag bit  
1= A write operation was prematurely terminated (any Reset during self-timed programming)  
0= The write operation completed normally  
Note:  
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows  
tracing of the error condition.  
bit 2  
bit 1  
WREN: Write Enable bit  
1= Allows erase or write cycles  
0= Inhibits erase or write cycles  
WR: Write Control bit  
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write  
cycle. (The operation is self-timed and the bit is cleared by hardware once write is  
complete. The WR bit can only be set (not cleared) in software.)  
0= Write cycle completed  
bit 0  
RD: Read Control bit  
1= Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can  
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)  
0= Read completed  
Legend:  
R = Readable bit  
S = Settable only  
U = Unimplemented bit, read as ‘0’ W = Writable bit  
‘0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR ‘1’ = Bit is set  
2003 Microchip Technology Inc.  
DS39599C-page 73  
 复制成功!