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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
FIGURE 6-2:  
TABLE WRITE OPERATION  
Instruction: TBLWT*  
Program Memory  
Holding Registers  
(1)  
Table Pointer  
Table Latch (8-bit)  
TABLAT  
TBLPTRU TBLPTRH TBLPTRL  
Program Memory  
(TBLPTR)  
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by  
TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in  
Section 6.5 “Writing to Flash Program Memory”.  
The WREN bit enables and disables erase and write  
operations. When set, erase and write operations are  
allowed. When clear, erase and write operations are  
disabled – the WR bit cannot be set while the WREN bit  
is clear. This process helps to prevent accidental writes  
to memory due to errant (unexpected) code execution.  
6.2  
Control Registers  
Several control registers are used in conjunction with  
the TBLRDand TBLWTinstructions. These include the:  
• EECON1 register  
• EECON2 register  
• TABLAT register  
• TBLPTR registers  
Firmware should keep the WREN bit clear at all times  
except when starting erase or write operations. Once  
firmware has set the WR bit, the WREN bit may be  
cleared. Clearing the WREN bit will not affect the  
operation in progress.  
6.2.1  
EECON1 AND EECON2 REGISTERS  
EECON1 is the control register for memory accesses.  
The WRERR bit is set when a write operation is inter-  
rupted by a Reset. In these situations, the user can  
check the WRERR bit and rewrite the location. It will be  
necessary to reload the data and address registers  
(EEDATA and EEADR) as these registers have cleared  
as a result of the Reset.  
EECON2 is not a physical register. Reading EECON2  
will read all ‘0’s. The EECON2 register is used  
exclusively in the memory write and erase sequences.  
Control bit, EEPGD, determines if the access will be to  
program or data EEPROM memory. When clear,  
operations will access the data EEPROM memory.  
When set, program memory is accessed.  
Control bits, RD and WR, start read and erase/write  
operations, respectively. These bits are set by firmware  
and cleared by hardware at the completion of the  
operation.  
Control bit, CFGS, determines if the access will be to  
the configuration registers or to program memory/data  
EEPROM memory. When set, subsequent operations  
access configuration registers. When CFGS is clear,  
the EEPGD bit selects either program Flash or data  
EEPROM memory.  
The RD bit cannot be set when accessing program  
memory (EEPGD = 1). Program memory is read using  
table read instructions. See Section 6.3 “Reading the  
Flash Program Memory” regarding table reads.  
The FREE bit controls program memory erase opera-  
tions. When the FREE bit is set, the erase operation is  
initiated on the next WR command. When FREE is  
clear, only writes are enabled.  
Note:  
Interrupt flag bit, EEIF in the PIR2 register,  
is set when the write is complete. It must  
be cleared in software.  
DS39599C-page 72  
2003 Microchip Technology Inc.  
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