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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
Since the Table Latch (TABLAT) is only a single byte,  
6.5  
Writing to Flash Program Memory  
the TBLWT instruction has to be executed 8 times for  
each programming operation. All of the table write  
operations will essentially be short writes because only  
the holding registers are written. At the end of updating  
8 registers, the EECON1 register must be written to, to  
start the programming operation with a long write.  
The programming block size is 4 words or 8 bytes.  
Word or byte programming is not supported.  
Table writes are used internally to load the holding reg-  
isters needed to program the Flash memory. There are  
8 holding registers used by the table writes for  
programming.  
The long write is necessary for programming the inter-  
nal Flash. Instruction execution is halted while in a long  
write cycle. The long write will be terminated by the  
internal programming timer.  
FIGURE 6-5:  
TABLE WRITES TO FLASH PROGRAM MEMORY  
TABLAT  
Write Register  
8
8
8
8
TBLPTR = xxxxx0  
TBLPTR = xxxxx2  
TBLPTR = xxxxx7  
Holding Register  
TBLPTR = xxxxx1  
Holding Register  
Holding Register  
Holding Register  
Program Memory  
8. Disable interrupts.  
6.5.1  
FLASH PROGRAM MEMORY WRITE  
SEQUENCE  
9. Write 55h to EECON2.  
10. Write AAh to EECON2.  
The sequence of events for programming an internal  
program memory location should be:  
11. Set the WR bit. This will begin the write cycle.  
12. The CPU will stall for duration of the write (about  
2 ms using internal timer).  
1. Read 64 bytes into RAM.  
2. Update data values in RAM as necessary.  
3. Load Table Pointer with address being erased.  
13. Execute a NOP.  
14. Re-enable interrupts.  
4. Do the row erase procedure (see Section 6.4.1  
“Flash Program Memory Erase Sequence”).  
15. Repeat steps 6-14 seven times, to write 64  
bytes.  
5. Load Table Pointer with address of first byte  
being written.  
16. Verify the memory (table read).  
This procedure will require about 18 ms to update one  
row of 64 bytes of memory. An example of the required  
code is given in Example 6-3.  
6. Write the first 8 bytes into the holding registers  
with auto-increment.  
7. Set the EECON1 register for the write operation:  
• set EEPGD bit to point to program  
memory;  
• clear the CFGS bit to access program  
memory;  
• set WREN bit to enable byte writes.  
2003 Microchip Technology Inc.  
DS39599C-page 77  
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