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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
6.4.1  
FLASH PROGRAM MEMORY  
ERASE SEQUENCE  
6.4  
Erasing Flash Program Memory  
The minimum erase block size is 32 words or 64 bytes  
under firmware control. Only through the use of an  
external programmer, or through ICSP control, can  
larger blocks of program memory be bulk erased. Word  
erase in Flash memory is not supported.  
The sequence of events for erasing a block of internal  
program memory location is:  
1. Load Table Pointer with address of row being  
erased.  
When initiating an erase sequence from the micro-  
controller itself, a block of 64 bytes of program memory  
is erased. The Most Significant 16 bits of the  
TBLPTR<21:6> point to the block being erased;  
TBLPTR<5:0> are ignored.  
2. Set the EECON1 register for the erase operation:  
• set EEPGD bit to point to program  
memory;  
• clear the CFGS bit to access program  
memory;  
The EECON1 register commands the erase operation.  
The EEPGD bit must be set to point to the Flash pro-  
gram memory. The CFGS bit must be clear to access  
program Flash and data EEPROM memory. The  
WREN bit must be set to enable write operations. The  
FREE bit is set to select an erase operation. The WR  
bit is set as part of the required instruction sequence  
(as shown in Example 6-2) and starts the actual erase  
operation. It is not necessary to load the TABLAT  
register with any data as it is ignored.  
• set WREN bit to enable writes;  
• set FREE bit to enable the erase.  
3. Disable interrupts.  
4. Write 55h to EECON2.  
5. Write AAh to EECON2.  
6. Set the WR bit. This will begin the row erase  
cycle.  
7. The CPU will stall for duration of the erase  
(about 2 ms using internal timer).  
For protection, the write initiate sequence using  
EECON2 must be used.  
8. Execute a NOP.  
9. Re-enable interrupts.  
A long write is necessary for erasing the internal Flash.  
Instruction execution is halted while in a long write  
cycle. The long write will be terminated by the internal  
programming timer.  
EXAMPLE 6-2:  
ERASING A FLASH PROGRAM MEMORY ROW  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
CODE_ADDR_UPPER  
TBLPTRU  
CODE_ADDR_HIGH  
TBLPTRH  
CODE_ADDR_LOW  
TBLPTRL  
; load TBLPTR with the base  
; address of the memory block  
ERASE_ROW  
BSF  
BSF  
BSF  
BCF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
EECON1,EEPGD  
EECON1,WREN  
EECON1,FREE  
INTCON,GIE  
55h  
EECON2  
AAh  
EECON2  
EECON2,WR  
; point to Flash program memory  
; enable write to memory  
; enable Row Erase operation  
; disable interrupts  
; write 55H  
Required  
Sequence  
; write AAH  
; start erase (CPU stall)  
NOP  
BSF  
INTCON,GIE  
; re-enable interrupts  
DS39599C-page 76  
2003 Microchip Technology Inc.  
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