PIC18F2220/2320/4220/4320
FIGURE 26-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 26-5 for load conditions.
FIGURE 26-9:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
TOST
MCLR Pulse Width (low)
2
3.48
—
4.00
—
—
4.71
µs
ms
—
31
32
33
34
Watchdog Timer Time-out Period (no postscaler)
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC
57.0
1024 TOSC
77.2
TOSC = OSC1 period
TPWRT
65.5
2
ms
µs
TIOZ
I/O High-Impedance from MCLR Low or
Watchdog Timer Reset
—
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
µs
µs
VDD ≤ BVDD (see D005)
VDD ≤ VLVD
TIVRST
Time for Internal Reference Voltage to become
stable
20
50
37
TLVD
Low-Voltage Detect Pulse Width
200
—
—
µs
DS39599C-page 328
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
