PIC18F2220/2320/4220/4320
26.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-6:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
CLKO
3
4
3
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
DC
DC
DC
0.1
4
40
25
4
MHz EC, ECIO (industrial)
MHz EC, ECIO (extended)
MHz RC osc
Oscillator Frequency(1)
1
MHz XT osc
25
10
6.25
33
—
—
—
—
MHz HS osc
4
MHz HS + PLL osc (industrial)
MHz HS + PLL osc (extended)
4
5
kHz
ns
LP Osc mode
EC, ECIO (industrial)
EC, ECIO (extended)
RC osc
1
TOSC
External CLKI Period(1)
Oscillator Period(1)
25
40
250
1
ns
ns
µs
XT osc
40
100
250
250
ns
ns
HS osc
HS + PLL osc (industrial)
160
30
250
—
ns
HS + PLL osc (extended)
LP osc
µs
2
3
TCY
Instruction Cycle Time(1)
100
160
—
—
ns
ns
TCY = 4/FOSC (industrial)
TCY = 4/FOSC (extended)
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
30
2.5
10
—
—
—
ns
µs
ns
ns
ns
ns
XT osc
LP osc
HS osc
XT osc
LP osc
HS osc
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2003 Microchip Technology Inc.
DS39599C-page 325
MICROCHIP [ MICROCHIP ]
