PIC18F2220/2320/4220/4320
REGISTER 2-2:
OSCCON REGISTER
R/W-0
IDLEN
R/W-0
IRCF2
R/W-0
IRCF1
R/W-0
IRCF0
R(1)
R-0
R/W-0
SCS1
R/W-0
SCS0
OSTS
IOFS
bit 7
bit 0
bit 7
IDLEN: Idle Enable bit
1= Idle mode enabled; CPU core is not clocked in power managed modes
0= Run mode enabled; CPU core is clocked in power managed modes
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111= 8 MHz (8 MHz source drives clock directly)
110= 4 MHz
101= 2 MHz
100= 1 MHz
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (INTRC source drives clock directly)
bit 3
bit 2
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator start-up time-out timer has expired; primary oscillator is running
0= Oscillator start-up time-out timer is running; primary oscillator is not ready
IOFS: INTOSC Frequency Stable bit
1= INTOSC frequency is stable
0= INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x= Internal oscillator block (RC modes)
01= Timer1 oscillator (Secondary modes)(2)
00= Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of IESO bit in Configuration Register 1H.
2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 26
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
