PIC18F2220/2320/4220/4320
2.6.2
INTRC OUTPUT FREQUENCY
2.6
Internal Oscillator Block
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
This changes the frequency of the INTRC source from
its nominal 31.25 kHz. Peripherals and features that
depend on the INTRC source will be affected by this
shift in frequency.
The PIC18F2X20/4X20 devices include an internal
oscillator block which generates two different clock sig-
nals. Either can be used as the system’s clock source.
This can eliminate the need for external oscillator
circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the system clock. It
also drives a postscaler which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
Once set during factory calibration, the INTRC
frequency will remain within ±1% as temperature and
VDD change across their full specified operating
ranges.
2.6.3
OSCTUNE REGISTER
The other clock source is the internal RC oscillator
(INTRC) which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source or when any of the
following are enabled:
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user's application.
This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
• Power-up Timer
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new fre-
quency within 8 clock cycles (approximately
8 * 32 µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred. Oper-
ation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 26).
2.6.1
INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
DS39599C-page 22
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
