欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F2320-I/SP的Datasheet PDF文件第25页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第26页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第27页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第28页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第30页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第31页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第32页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第33页  
PIC18F2220/2320/4220/4320  
If the Sleep mode is selected, all clock sources are  
stopped. Since all the transistor switching currents  
have been stopped, Sleep mode achieves the lowest  
current consumption of the device (only leakage  
currents).  
2.7.2  
OSCILLATOR TRANSITIONS  
The PIC18F2X20/4X20 devices contain circuitry to pre-  
vent clocking “glitches” when switching between clock  
sources. A short pause in the system clock occurs dur-  
ing the clock switch. The length of this pause is  
between 8 and 9 clock periods of the new clock source.  
This ensures that the new clock source is stable and  
that its pulse width will not be less than the shortest  
pulse width of the two clock sources.  
Enabling any on-chip feature that will operate during  
Sleep will increase the current consumed during Sleep.  
The INTRC is required to support WDT operation. The  
Timer1 oscillator may be operating to support a real-  
time clock. Other features may be operating that do not  
require a system clock source (i.e., SSP slave, PSP,  
INTn pins, A/D conversions and others).  
Clock transitions are discussed in greater detail in  
Section 3.1.2 “Entering Power Managed Modes”.  
2.8  
Effects of Power Managed Modes  
on the Various Clock Sources  
2.9  
Power-up Delays  
Power-up delays are controlled by two timers so that no  
external Reset circuitry is required for most applica-  
tions. The delays ensure that the device is kept in  
Reset until the device power supply is stable under nor-  
mal circumstances and the primary clock is operating  
and stable. For additional information on power-up  
delays, see Section 4.1 “Power-on Reset (POR)”  
through Section 4.5 “Brown-out Reset (BOR)”.  
When the device executes a SLEEP instruction, the  
system is switched to one of the power managed  
modes, depending on the state of the IDLEN and  
SCS1:SCS0 bits of the OSCCON register. See  
Section 3.0 “Power Managed Modes” for details.  
When PRI_IDLE mode is selected, the designated pri-  
mary oscillator continues to run without interruption.  
For all other power managed modes, the oscillator  
using the OSC1 pin is disabled. The OSC1 pin (and  
OSC2 pin, if used by the oscillator) will stop oscillating.  
The first timer is the Power-up Timer (PWRT) which  
provides a fixed delay on power-up (parameter 33,  
Table 26-10), if enabled, in Configuration Register 2L.  
The second timer is the Oscillator Start-up Timer  
(OST), intended to keep the chip in Reset until the crys-  
tal oscillator is stable (LP, XT and HS modes). The OST  
does this by counting 1024 oscillator cycles before  
allowing the oscillator to clock the device.  
In secondary clock modes (SEC_RUN and  
SEC_IDLE), the Timer1 oscillator is operating and pro-  
viding the system clock. The Timer1 oscillator may also  
run in all power managed modes if required to clock  
Timer1 or Timer3.  
In internal oscillator modes (RC_RUN and RC_IDLE),  
the internal oscillator block provides the system clock  
source. The INTRC output can be used directly to  
provide the system clock and may be enabled to  
support various special features, regardless of the  
power managed mode (see Section 23.2 “Watchdog  
Timer (WDT)” through Section 23.4 “Fail-Safe Clock  
Monitor”). The INTOSC output at 8 MHz may be used  
directly to clock the system or may be divided down  
first. The INTOSC output is disabled if the system clock  
is provided directly from the INTRC output.  
When the HSPLL Oscillator mode is selected, the  
device is kept in Reset for an additional 2 ms, following  
the HS mode OST delay, so the PLL can lock to the  
incoming clock frequency.  
There is a delay of 5 to 10 µs, following POR, while the  
controller becomes ready to execute instructions. This  
delay runs concurrently with any other delays. This  
may be the only delay that occurs when any of the EC,  
RC or INTIO modes are used as the primary clock  
source.  
TABLE 2-3:  
OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
OSC Mode  
OSC1 Pin  
OSC2 Pin  
RC, INTIO1  
Floating, external resistor  
should pull high  
At logic low (clock/4 output)  
RCIO, INTIO2  
Floating, external resistor  
should pull high  
Configured as PORTA, bit 6  
ECIO  
Floating, pulled by external clock  
Floating, pulled by external clock  
Configured as PORTA, bit 6  
At logic low (clock/4 output)  
EC  
LP, XT, and HS  
Feedback inverter disabled at  
quiescent voltage level  
Feedback inverter disabled at  
quiescent voltage level  
Note:  
See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.  
2003 Microchip Technology Inc.  
DS39599C-page 27  
 复制成功!