PIC18F2220/2320/4220/4320
3.1.2
ENTERING POWER MANAGED
MODES
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration Register 1H), the secondary
clock (the Timer1 oscillator) and the internal oscillator
block (used in RC modes). Modifying the SCS bits will
have no effect until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEPinstruction.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a trigger to place the controller into
a power managed mode selected by the
OSCCON register, one of which is Sleep
mode.
3.1.3
MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEPinstruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power managed mode specified by
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscilla-
tor. When the SLEEPinstruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is between eight and nine clock periods from the
new clock source. This ensures that the new clock
source is stable and that its pulse width will not be less
than the shortest pulse width of the two clock sources.
3.1.4
COMPARISONS BETWEEN RUN
AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEPinstruc-
tion is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a change of clock source at the time a
SLEEPinstruction is executed, a clock switch will occur.
Three bits indicate the current clock source: OSTS and
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one of these bits will be set while
in a power managed mode other than PRI_RUN. When
the OSTS bit is set, the primary clock is providing the
system clock. When the IOFS bit is set, the INTOSC
output is providing a stable 8 MHz clock source and is
providing the system clock. When the T1RUN bit is set,
the Timer1 oscillator is providing the system clock. If
none of these bits are set, then either the INTRC clock
source is clocking the system or the INTOSC source is
not yet stable.
In Idle modes, the CPU is not clocked and is not run-
ning. In Run modes, the CPU is clocked and executing
code. This difference modifies the operation of the
WDT when it times out. In Idle modes, a WDT time-out
results in a wake from power managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).
During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode until the primary clock becomes ready. When the
primary clock becomes ready, the clock source is auto-
matically switched to the primary clock. The IDLEN and
SCS bits are unchanged during and after the wake-up.
If the internal oscillator block is configured as the pri-
mary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering a power managed RC mode
(same frequency) would clear the OSTS bit.
Figure 3-2 shows how the system is clocked during the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).
DS39599C-page 30
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
