PIC18F2220/2320/4220/4320
COMF
Complement f
CPFSEQ
Compare f with W, skip if f = W
Syntax:
[ label ] COMF f [,d [,a]]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
Operation:
(f) → dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched instruc-
tion is discarded and a NOPis
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
Write to
1(2)
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
REG, W
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
0x13
W
=
0xEC
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
W
REG
=
=
?
?
After Instruction
If REG
PC
=
=
W;
Address (EQUAL)
If REG
PC
≠
=
W;
Address (NEQUAL)
DS39599C-page 272
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
