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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
CPFSGT  
Compare f with W, skip if f > W  
CPFSLT  
Compare f with W, skip if f < W  
Syntax:  
[ label ] CPFSGT f [,a]  
Syntax:  
[ label ] CPFSLT f [,a]  
Operands:  
0 f 255  
a [0,1]  
Operands:  
0 f 255  
a [0,1]  
Operation:  
(f) − (W),  
Operation:  
(f) – (W),  
skip if (f) > (W)  
(unsigned comparison)  
skip if (f) < (W)  
(unsigned comparison)  
Status Affected:  
Encoding:  
None  
Status Affected:  
Encoding:  
None  
0110  
010a  
ffff  
ffff  
0110  
000a  
ffff  
ffff  
Description:  
Compares the contents of data  
memory location 'f' to the contents  
of the W by performing an  
Description:  
Compares the contents of data  
memory location ‘f’ to the contents  
of W by performing an unsigned  
subtraction.  
unsigned subtraction.  
If the contents of ‘f’ are greater than  
the contents of WREG, then the  
fetched instruction is discarded and  
a NOPis executed instead, making  
this a two-cycle instruction. If ‘a’ is  
0’, the Access Bank will be  
selected, overriding the BSR value.  
If ‘a’ = 1, then the bank will be  
selected as per the BSR value  
(default).  
If the contents of ‘f’ are less than  
the contents of W, then the fetched  
instruction is discarded and a NOP  
is executed instead, making this a  
two-cycle instruction. If ‘a’ is ‘0’, the  
Access Bank will be selected. If ’a’  
is ‘1’, the BSR will not be  
overridden (default).  
Words:  
Cycles:  
1
1(2)  
Words:  
Cycles:  
1
Note: 3 cycles if skip and followed  
by a 2-word instruction.  
1(2)  
Note: 3 cycles if skip and followed  
by a 2-word instruction.  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Q Cycle Activity:  
Q1  
Decode  
Read  
register ‘f’  
Process  
Data  
No  
operation  
Q2  
Q3  
Q4  
Decode  
Read  
register ‘f’  
Process  
Data  
No  
operation  
If skip:  
Q1  
Q2  
Q3  
Q4  
If skip:  
Q1  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
Q2  
Q3  
Q4  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
If skip and followed by 2-word instruction:  
Q1  
Q2  
Q3  
Q4  
If skip and followed by 2-word instruction:  
No  
No  
No  
No  
Q1  
Q2  
Q3  
Q4  
operation  
operation  
operation  
operation  
No  
No  
No  
No  
No  
No  
No  
No  
operation  
operation  
operation  
operation  
operation  
operation  
operation  
operation  
No  
No  
No  
No  
operation  
operation  
operation  
operation  
HERE  
NLESS  
LESS  
CPFSLT REG  
:
:
Example:  
HERE  
CPFSGT REG  
Example:  
NGREATER  
GREATER  
:
:
Before Instruction  
PC  
W
=
=
Address (HERE)  
?
Before Instruction  
After Instruction  
PC  
W
=
=
Address (HERE)  
?
If REG  
PC  
If REG  
PC  
<
=
=
W;  
Address (LESS)  
W;  
Address (NLESS)  
After Instruction  
If REG  
PC  
>
=
W;  
Address (GREATER)  
If REG  
PC  
=
W;  
Address (NGREATER)  
2003 Microchip Technology Inc.  
DS39599C-page 273  
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