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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
An external clock source may also be connected to the  
OSC1 pin in the HS mode, as shown in Figure 2-2.  
TABLE 2-2:  
CAPACITOR SELECTION FOR  
CRYSTAL OSCILLATOR  
Typical Capacitor Values  
FIGURE 2-2:  
EXTERNAL CLOCK INPUT  
OPERATION (HS OSC  
CONFIGURATION)  
Crystal  
Freq  
Tested:  
Osc Type  
C1  
C2  
LP  
XT  
HS  
32 kHz  
200 kHz  
1 MHz  
4 MHz  
4 MHz  
8 MHz  
20 MHz  
33 pF  
15 pF  
33 pF  
27 pF  
27 pF  
22 pF  
15 pF  
33 pF  
15 pF  
33 pF  
27 pF  
27 pF  
22 pF  
15 pF  
OSC1  
Clock from  
Ext. System  
PIC18FXXXX  
(HS Mode)  
OSC2  
Open  
2.3  
HSPLL  
Capacitor values are for design guidance only.  
A Phase Locked Loop (PLL) circuit is provided as an  
option for users who wish to use a lower frequency  
crystal oscillator circuit, or to clock the device up to its  
highest rated frequency from a crystal oscillator. This  
may be useful for customers who are concerned with  
EMI due to high-frequency crystals.  
These capacitors were tested with the crystals listed  
below for basic start-up and operation. These values  
are not optimized.  
Different capacitor values may be required to produce  
acceptable oscillator operation. The user should test  
the performance of the oscillator over the expected  
VDD and temperature range for the application.  
The HSPLL mode makes use of the HS mode oscillator  
for frequencies up to 10 MHz. A PLL then multiplies the  
oscillator output frequency by 4 to produce an internal  
clock frequency up to 40 MHz.  
See the notes following this table for additional  
information.  
The PLL is enabled only when the oscillator configura-  
tion bits are programmed for HSPLL mode. If  
programmed for any other mode, the PLL is not  
enabled.  
Crystals Used:  
32 kHz  
200 kHz  
1 MHz  
4 MHz  
8 MHz  
20 MHz  
FIGURE 2-3:  
PLL BLOCK DIAGRAM  
HS Osc Enable  
PLL Enable  
(from Configuration Register 1H)  
Note 1: Higher capacitance increases the stability  
of the oscillator, but also increases the  
start-up time.  
2: When operating below 3V VDD, or when  
using certain ceramic resonators at any  
voltage, it may be necessary to use the  
HS mode or switch to a crystal oscillator.  
OSC2  
OSC1  
Phase  
Comparator  
HS Mode  
Crystal  
Osc  
FIN  
FOUT  
3: Since each resonator/crystal has its own  
characteristics, the user should consult  
the resonator/crystal manufacturer for  
Loop  
Filter  
appropriate  
values  
of  
external  
components.  
÷4  
VCO  
4: RS may be required to avoid overdriving  
SYSCLK  
crystals with low drive level specification.  
5: Always verify oscillator performance over  
the VDD and temperature range that is  
expected for the application.  
DS39599C-page 20  
2003 Microchip Technology Inc.