PIC18F2220/2320/4220/4320
19.5 Operation in Power Managed
Modes
19.6 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power managed mode.
If the A/D is expected to operate while the device is in
a power managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power managed mode clock that
will be used. After the power managed mode is entered
(either of the power managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power managed Idle mode during the
conversion.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
If the power managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
3: The PBADEN bit in the Configuration
register configures PORTB pins to reset
as analog or digital pins by controlling
how the PCFG0 bits in ADCON1 are
reset.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
DS39599C-page 218
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
