PIC18F2220/2320/4220/4320
20.1 Comparator Configuration
20.0 COMPARATOR MODULE
There are eight modes of operation for the comparators.
The CM bits (CMCON<2:0>) are used to select these
modes. Figure 20-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator mode
is changed, the comparator output level may not be valid
for the specified mode change delay shown in the
Electrical Specifications (see Section 26.0 “Electrical
Characteristics”).
The comparator module contains two analog compara-
tors. The inputs and outputs for the comparators are
multiplexed with the RA0 through RA5 pins. The on-
chip voltage reference (Section 21.0 “Comparator
Voltage Reference Module”) can also be an input to
the comparators.
The CMCON register, shown as Register 20-1,
controls the comparator module’s input and output
multiplexers.
A
block diagram of the various
comparator configurations is shown in Figure 20-1.
Note:
Comparator interrupts should be disabled
during Comparator mode change.
Otherwise, a false interrupt may occur.
a
REGISTER 20-1: CMCON REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-1
CM2
R/W-1
CM1
R/W-1
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0= C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
2003 Microchip Technology Inc.
DS39599C-page 221
MICROCHIP [ MICROCHIP ]
