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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
The ECCP module differs from the CCP with the addi-  
tion of an enhanced PWM mode which allows for 2 or  
4 output channels, user-selectable polarity, dead band  
control and automatic shutdown and restart. These  
features are discussed in detail in Section 16.4  
16.0 ENHANCED CAPTURE/  
COMPARE/PWM (ECCP)  
MODULE  
Note:  
The ECCP (Enhanced Capture/ Compare/  
“Enhanced PWM Mode”.  
PWM) module is only available on  
PIC18F4X20 devices.  
The control register for CCP1 is shown in Register 16-1.  
It differs from the CCP1CON register of PIC18F2X20  
devices in that the two Most Significant bits are  
implemented to control enhanced PWM functionality.  
In 40 and 44-pin devices, the CCP1 module is  
implemented as standard CCP module with  
a
enhanced PWM capabilities. Operation of the Capture,  
Compare and standard single output PWM modes is  
described in Section 15.0 “Capture/Compare/PWM  
(CCP) Modules”. Discussion in that section relating to  
PWM frequency and duty cycle also apply to the  
enhanced PWM mode.  
REGISTER 16-1: CCP1CON REGISTER FOR ENHANCED CCP OPERATION (PIC18F4X20 ONLY)  
R/W-0  
P1M1  
R/W-0  
P1M0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
DC1B1  
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0  
bit 0  
bit 7  
bit 7-6  
P1M1:P1M0: PWM Output Configuration bits  
If CCP1M<3:2> = 00, 01, 10(Capture, Compare, or disabled):  
xx=P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins  
If CCP1M<3:2> = 11(PWM modes):  
00=Single output; P1A modulated; P1B, P1C, P1D assigned as port pins  
01=Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive  
10= Half-bridge output; P1A, P1B modulated with dead band control; P1C, P1D assigned as port pins  
11=Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive  
bit 5-4  
DC1B1:DC1B0: PWM Duty Cycle Least Significant bits  
Capture mode:  
Unused.  
Compare mode:  
Unused.  
PWM mode:  
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.  
bit 3-0  
CCP1M3:CCP1M0: ECCP1 Mode Select bits  
0000= Capture/Compare/PWM off (resets ECCP module)  
0001= Unused (reserved)  
0010= Compare mode, toggle output on match (ECCP1IF bit is set)  
0011= Unused (reserved)  
0100= Capture mode, every falling edge  
0101= Capture mode, every rising edge  
0110= Capture mode, every 4th rising edge  
0111= Capture mode, every 16th rising edge  
1000= Compare mode, set output on match (ECCP1IF bit is set)  
1001= Compare mode, clear output on match (ECCP1IF bit is set)  
1010= Compare mode, generate software interrupt on match (ECCP1IF bit is set, ECCP1 pin  
operates as a port pin for input and output)  
1011= Compare mode, trigger special event (ECCP1IF bit is set, ECCP resets TMR1or TMR2  
and starts an A/D conversion if the A/D module is enabled)  
1100= PWM mode, P1A, P1C active-high, P1B, P1D active-high  
1101= PWM mode, P1A, P1C active-high, P1B, P1D active-low  
1110= PWM mode, P1A, P1C active-low, P1B, P1D active-high  
1111= PWM mode, P1A, P1C active-low, P1B, P1D active-low  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR  
2003 Microchip Technology Inc.  
DS39599C-page 141  
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