PIC18F2220/2320/4220/4320
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
15.5.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and the CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
EQUATION 15-3:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
FOSC
FPWM
log
5. Configure the CCP1 module for PWM operation.
bits
PWM Resolution (max) =
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
TXIE
TXIP
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 Module Register
0000 0000 0000 0000
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
CCPR1L
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB)
CCP1CON
CCPR2L
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 2 (LSB)
CCPR2H Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
OSCCON
—
—
DC2B1
IRCF1
DC2B0
IRCF0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
IDLEN
IRCF2
OSTS
IOFS
SCS1
SCS0
0000 qq00 0000 qq00
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 139
MICROCHIP [ MICROCHIP ]
