PIC18F2220/2320/4220/4320
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
LATB
0x0F
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
RB3 can be configured by the configuration bit,
CCP2MX, as the alternate peripheral pin for the CCP2
module (CCP2MX = 0).
CLRF
FIGURE 10-6:
BLOCK DIAGRAM OF
RB7:RB5 PINS
MOVLW
MOVWF
; Set RB<4:0> as
ADCON1 ; digital I/O pins
; (required if config bit
VDD
RBPU(2)
Data Bus
Weak
Pull-up
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
P
MOVLW
MOVWF
0xCF
Data Latch
D
Q
WR LATB
or PORTB
I/O pin(1)
TRISB
CK
TRIS Latch
D
Q
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
WR TRISB
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Note:
On a Power-on Reset, RB4:RB0 are con-
figured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
Latch
Q
Q
D
RD PORTB
Set RBIF
EN
Q1
By programming the configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be configured as digital inputs
on POR.
D
RD PORTB
Q3
From other
RB7:RB5 and
RB4 pins
EN
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
RB7:RB5 in Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
DS39599C-page 104
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
