PIC18F2220/2320/4220/4320
TABLE 10-1: PORTA FUNCTIONS
Name
Bit#
Buffer
Function
Input/output or analog input.
RA0/AN0
RA1/AN1
bit 0
bit 1
bit 2
bit 3
bit 4
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Input/output, analog input, VREF- or Comparator VREF output.
Input/output, analog input or VREF+.
RA4/T0CKI/C1OUT
Input/output, external clock input for Timer0 or Comparator 1
output. Output is open-drain type.
RA5/AN4/SS/LVDIN/C2OUT
bit 5
TTL
Input/output, analog input, Slave Select input for Synchronous
Serial Port, Low-Voltage Detect input or Comparator 2 output.
OSC2/CLKO/RA6
OSC1/CLKI/RA7
bit 6
bit 7
TTL
TTL
OSC2, clock output or I/O pin.
OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000 uu0u 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
(1)
(1)
LATA
LATA7
LATA6
LATA Data Latch Register
(1)
(1)
TRISA
TRISA7
—
TRISA6
—
PORTA Data Direction Register
ADCON1
CMCON
CVRCON
VCFG1
C2INV
CVRR
VCFG0
C1INV
—
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
PCFG0 --00 0000 --00 0000
C2OUT
CVREN
C1OUT
CVROE
CM0
0000 0111 0000 0111
000- 0000 000- 0000
CVR3
CVR2
CVR1
CVR0
Legend: x= unknown, u= unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
2003 Microchip Technology Inc.
DS39599C-page 103
MICROCHIP [ MICROCHIP ]
