PIC18F2220/2320/4220/4320
10.1 PORTA, TRISA and LATA
Registers
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate func-
tion from the peripheral features on the device. In gen-
eral, when a peripheral is enabled, that pin may not be
used as a general purpose I/O pin.
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Each port has three registers for its operation. These
registers are:
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
• LAT register (Data Latch)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in Configuration Register 1H (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 10-1.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the com-
parator voltage reference output. The operation of pins,
RA3:RA0 and RA5, as A/D converter inputs is selected
by clearing/setting the control bits in the ADCON1 reg-
ister (A/D Control Register 1). Pins RA0 through RA5
may also be used as comparator inputs or outputs by
setting the appropriate bits in the CMCON register.
RD LAT
Data
Bus
D
Q
WR LAT
I/O pin(1)
or
Port
CK
Data Latch
D
Q
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input
and an open-drain output. All other PORTA pins have
TTL input levels and full CMOS output drivers.
The TRISA register controls the direction of the RA pins
even when they are being used as analog inputs. The
user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Q
D
EN
EN
RD Port
EXAMPLE 10-1:
INITIALIZING PORTA
Note 1: I/O pins have diode protection to VDD and VSS.
CLRF
PORTA
LATA
0x07
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
2003 Microchip Technology Inc.
DS39599C-page 101
MICROCHIP [ MICROCHIP ]
