PIC17C4X
6.1.2
EXTERNAL MEMORY INTERFACE
In extended microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
When either microprocessor or extended microcontrol-
ler mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE is for the
control signals. External components are needed to
demultiplex the address and data. This can be done as
shown in Figure 6-4. The waveforms of address and
data are shown in Figure 6-3. For complete timings,
please refer to the electrical specification section.
This following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers mem-
ory, please refer to the electrical specifications of the
desired PIC17C4X device, as well as the desired mem-
ory device to ensure compatibility.
TABLE 6-2:
EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
FIGURE 6-3: EXTERNAL PROGRAM
MEMORY ACCESS
WAVEFORMS
EPROM Suffix
Q1 Q2
Q4 Q1 Q2
Q4 Q1
Data out
Q3
Q3
PIC17C4X Instruction
Oscillator Cycle
Frequency Time (TCY) PIC17C42 PIC17C44
AD
<15:0>
PIC17C43
Address out Data in
Address out
ALE
OE
8 MHz
16 MHz
20 MHz
25 MHz
33 MHz
500 ns
250 ns
200 ns
160 ns
121 ns
-25
-12
-25
-15
-10
-70
(1)
'1'
WR
Read cycle
Write cycle
-90
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
N.A.
N.A.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 6-2 lists external memory speed requirements for
a given PIC17C4X device frequency.
Note 1: The access times for this requires the use of
fast SRAMS.
Note: The external memory interface is not sup-
ported for the LC devices.
FIGURE 6-4: TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
Memory
(LSB)
Memory
(MSB)
A15-A0
AD7-AD0
PIC17C4X
373
373
Ax-A0
D7-D0
Ax-A0
D7-D0
CE
CE
(2)
(2)
OE WR
OE WR
AD15-AD8
ALE
(1)
138
(1)
I/O
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
1996 Microchip Technology Inc.
DS30412C-page 31
MICROCHIP [ MICROCHIP ]
