PIC17C4X
TABLE 6-3:
SPECIAL FUNCTION REGISTERS
Value on
Power-on
Reset
Value on all
other
resets (3)
Address Name
Unbanked
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
01h
02h
INDF0
FSR0
Uses contents of FSR0 to address data memory (not a physical register)
Indirect data memory address pointer 0
Low order 8-bits of PC
---- ---- ---- ----
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
PCL
03h(1)
04h
PCLATH
ALUSTA
T0STA
Holding register for upper 8-bits of PC
FS3
FS2
FS1
FS0
PS3
OV
Z
DC
C
1111 xxxx 1111 uuuu
0000 000- 0000 000-
05h
INTEDG
T0SE
T0CS
PS2
PS1
PS0
—
06h(2)
07h
—
—
STKAV
T0IF
GLINTD
INTF
TO
PD
—
—
--11 11-- --11 qq--
CPUSTA
INTSTA
INDF1
PEIF
T0CKIF
PEIE
T0CKIE
T0IE
INTE
0000 0000 0000 0000
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
08h
Uses contents of FSR1 to address data memory (not a physical register)
Indirect data memory address pointer 1
Working register
09h
FSR1
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
TMR0 register; low byte
TMR0 register; high byte
Low byte of program memory table pointer
High byte of program memory table pointer
Bank select register
(4)
(4)
(4)
(4)
0000 0000 0000 0000
Bank 0
10h
PORTA
DDRB
RBPU
—
RA5
RA4
RA3
RA2
RA1/T0CKI RA0/INT 0-xx xxxx 0-uu uuuu
1111 1111 1111 1111
11h
Data direction register for PORTB
PORTB data latch
12h
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
xxxx xxxx uuuu uuuu
13h
SPEN
Serial port receive register
CSRC TX9 TXEN
RX9
SREN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h
15h
16h
Serial port transmit register
Baud rate generator register
17h
Bank 1
10h
DDRC
PORTC
DDRD
PORTD
DDRE
Data direction register for PORTC
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- -111 ---- -111
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
11h
12h
13h
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
14h
15h
16h
17h
Data direction register for PORTE
PORTE
PIR
—
—
—
—
—
RE2/WR
CA1IF
RE1/OE
TXIF
RE0/ALE ---- -xxx ---- -uuu
RBIF
RBIE
TMR3IF
TMR2IF
TMR1IF
TMR1IE
CA2IF
CA2IE
RCIF
RCIE
0000 0010 0000 0010
0000 0000 0000 0000
PIE
TMR3IE TMR2IE
CA1IE
TXIE
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2:
3:
4:
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
The following values are for both TBLPTRL and TBLPTRH:
All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)
except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)
The PRODL and PRODH registers are not implemented on the PIC17C42.
5:
DS30412C-page 34
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
