PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
121
121
RA4/RX/DT
pin
122
120
TABLE 19-9: SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units Conditions
120
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
PIC17CR42/42A/43/R43/44
PIC17LCR42/42A/43/R43/44
—
—
—
—
—
—
—
—
—
—
—
—
50
75
25
40
25
40
ns
ns
ns
ns
ns
ns
Clock high to data out valid
121
122
†
TckRF
TdtRF
Clock out rise time and fall time PIC17CR42/42A/43/R43/44
(Master Mode)
PIC17LCR42/42A/43/R43/44
Data out rise time and fall time PIC17CR42/42A/43/R43/44
PIC17LCR42/42A/43/R43/44
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 19-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RA5/TX/CK
125
pin
RA4/RX/DT
pin
126
TABLE 19-10: SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
15
—
—
ns
Data hold before CK↓ (DT hold time)
126
TckL2dtl
Data hold after CK↓ (DT hold time)
15
—
—
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1996 Microchip Technology Inc.
DS30412C-page 189
MICROCHIP [ MICROCHIP ]
