PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-12: MEMORY INTERFACE READ TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES)
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
161
Data in
162
AD<15:0>
WR
Addr out
150
Addr out
151
163
167
'1'
'1'
TABLE 19-12: MEMORY INTERFACE READ REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X
DEVICES)
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
150
TadV2alL
AD15:AD0 (address) valid to ALE↓
0.25Tcy - 10
—
—
ns
(address setup time)
151
TalL2adI
ALE↓ to address out invalid
5*
—
—
ns
(address hold time)
160
161
162
TadZ2oeL
AD15:AD0 hi-impedance to OE↓
0*
0.25Tcy - 15
35
—
—
—
—
—
—
ns
ns
ns
ToeH2adD OE↑ to AD15:AD0 driven
TadV2oeH Data in valid before OE↑
(data setup time)
163
164
ToeH2adI
TalH
OE↑to data in invalid (data hold time)
0
—
—
—
ns
ns
ALE pulse width
—
0.25TCY §
165
166
167
ToeL
OE pulse width
0.5Tcy - 35 §
—
TCY §
—
—
—
ns
ns
ns
TalH2alH
Tacc
ALE↑ to ALE↑(cycle time)
Address access time
—
—
0.75TCY - 30
168
Toe
Output enable access time
(OE low to Data Valid)
—
—
0.5TCY - 45
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 191
MICROCHIP [ MICROCHIP ]
