PIC17C75X
FIGURE 3-1: PIC17C75X BLOCK DIAGRAM
PORTA
Clock
Generator
OSC1,
OSC2
Q1, Q2,
Q3, Q4
RA0/INT
RA1/T0CKI
IR<16>
Power-on
Reset
BITOP
WREG<8>
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
Brown-out
Reset
VDD, VSS
Chip_reset
& Other
Control
Watchdog
Timer
MCLR, VSS
Test
PORTB
8 x 8 mult
ALU
Signals
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
Test Mode
Select
PRODH PRODL
Shifter
IR Latch <16>
8
8
RB7/SDO
IR<7>
PORTC
8
BSR <7:4>
IR <7:0>
16
F1
F9
Decode
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
12
Read/write
Decode
for
Instruction
Decode
RAM
Address
Buffer
Data RAM
17C756
902 x 8
Registers
ROM Latch <16>
Mapped
in Data
Space
8
Control Outputs
17C752
454 x 8
PORTD
RD0/AD8
RD1/AD9
AD<15:0>
PORTC,
PORTD
Data Latch
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
Literal
BSR
Table
Latch <16>
Data Latch
Program
Memory
(EPROM)
17C756
16K x 16
PORTE
17C752
8K x 16
RE0/ALE
RE1/OE
RE2/WR
ALE,
WR,
OE,
Address
Latch
Table Pointer<16>
Stack
PCLATH<8>
RE3/CAP4
PORTE
16
16
PORTF
PCH
PCL
16
16 x 16
16
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
Data Bus<8>
10-bit
A/D
Timer0
Timer2
Timer3
PWM1
PWM2
PWM3
Capture2
SSP
IR<7>
USART1
USART2
PORTG
RG0/AN3
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
Interrupt
Module
Timer1
Capture1 Capture3 Capture4
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
DS30264A-page 10
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
