PIC16F913/914/916/917/946
TABLE 2-4:
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 3
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
41,226
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
OPTION_REG
PCL
RBPU
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
33,227
40,226
32,226
STATUS
PD
Z
DC
C
FSR
41,226
81,228
TRISF(3)
TRISB
TRISF7
TRISB7
—
TRISF6
TRISB6
—
TRISF5
TRISB5
TRISG5
RF5
TRISF4
TRISB4
TRISG4
RF4
TRISF3
TRISB3
TRISG3
RF3
TRISF2
TRISB2
TRISG2
RF2
TRISF1
TRISB1
TRISG1
RF1
TRISF0 1111 1111
TRISB0 1111 1111
TRISG0 --11 1111
54,227
84,228
81,228
84,228
TRISG(3)
PORTF(3)
PORTG(3)
PCLATH
INTCON
EECON1
EECON2
RF7
RF6
—
RF0
RG0
xxxx xxxx
--xx xxxx
—
RG5
RG4
RG3
RG2
RG1
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
0--- x000
---- ----
40,226
34,226
189,229
187
GIE
PEIE
—
T0IE
INTE
—
RBIE
T0IF
INTF
WR
RBIF
RD
EEPGD
—
WRERR
WREN
EEPROM Control Register 2 (not a physical register)
18Eh
18Fh
190h
—
—
Reserved
Reserved
—
—
—
—
LCDDATA12(3) SEG31
COM0
LCDDATA13(3) SEG39
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24
COM0
xxxx xxxx
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
SEG38
COM0
SEG37
COM0
SEG36
COM0
SEG35
COM0
SEG34
COM0
SE33
COM0
SEG32
COM0
xxxx xxxx
---- --xx
xxxx xxxx
xxxx xxxx
---- --xx
xxxx xxxx
xxxx xxxx
---- --xx
xxxx xxxx
xxxx xxxx
---- --xx
LCDDATA14(3)
—
—
—
—
—
—
SEG41
COM0
SEG40
COM0
LCDDATA15(3) SEG31
COM1
LCDDATA16(3) SEG39
COM1
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24
COM1
SEG38
COM1
SEG37
COM1
SEG36
COM1
SEG35
COM1
SEG34
COM1
SEG33
COM1
SEG32
COM1
LCDDATA17(3)
—
—
—
—
—
—
SEG41
COM1
SEG40
COM1
LCDDATA18(3) SEG31
COM2
LCDDATA19(3) SEG39
COM2
SEG30
COM2
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24
COM2
SEG38
COM2
SEG37
COM2
SEG36
COM2
SEG35
COM2
SEG34
COM2
SEG33
COM2
SEG32
COM2
LCDDATA20(3)
—
—
—
—
—
—
SEG41
COM2
SEG40
COM2
LCDDATA21(3) SEG31
COM3
LCDDATA22(3) SEG39
COM3
SEG30
COM3
SEG29
COM3
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24
COM3
SEG38
COM3
SEG37
COM3
SEG36
COM3
SEG35
COM3
SEG34
COM3
SEG33
COM3
SEG32
COM3
LCDDATA23(3)
—
—
—
—
—
—
SEG41
COM3
SEG40
COM3
19Ch
19Dh
LCDSE3(2, 3)
LCDSE4(2, 3)
SE31
SE39
—
SE30
SE38
—
SE29
SE37
—
SE28
SE36
—
SE27
SE35
—
SE26
SE34
—
SE25
SE33
SE41
SE24
SE32
SE40
0000 0000
0000 0000
147,229
147,229
19Eh
19Fh
LCDSE5(2, 3)
—
---- --00
147,229
—
Unimplemented
—
Legend:
Note 1:
–= Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
PIC16F946 only.
2:
3:
© 2007 Microchip Technology Inc.
DS41250F-page 31
MICROCHIP [ MICROCHIP ]
