PIC16F87/88
Checking the state of the OSTS bit will confirm
whether the primary clock configuration is engaged. If
not, the OSTS bit will remain clear.
15.12.3 TWO-SPEED CLOCK START-UP
MODE
Two-Speed Start-up mode minimizes the latency
between oscillator start-up and code execution that
may be selected with the IESO (Internal/External
Switch Over) bit in Configuration Word 2. This mode is
achieved by initially using the INTRC for code
execution until the primary oscillator is stable.
When the device is auto-configured in INTRC mode fol-
lowing a POR or wake-up from SLEEP, the rules for
entering other oscillator modes still apply, meaning the
SCS<1:0> bits in OSCCON can be modified before the
OST time-out has occurred. This would allow the appli-
cation to wake-up from SLEEP, perform a few instruc-
tions using the INTRC as the clock source and go back
to SLEEP without waiting for the primary oscillator to
become stable.
If this mode is enabled, and any of the following condi-
tions exist, the system will begin execution with the
INTRC oscillator. This results in almost immediate
code execution with a minimum of delay.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit to remain clear.
• POR and after the Power-up Timer has expired (if
PWRTEN = 0),
• or following a wake-up from SLEEP,
• or a RESET when running from T1OSC or INTRC
(after a RESET, SCS<1:0> are always set to ‘00’).
15.12.3.1 Two-Speed Start-up Mode
Sequence
1. Wake-up from SLEEP, RESET, or POR.
Note:
Following any RESET, the IRCF bits are
zeroed and the frequency selection is
forced to 31.25 kHz. The user can modify
the IRCF bits to select a higher internal
oscillator frequency.
2. OSCON bits configured to run from INTRC
(31.25 kHz).
3. Instructions begin execution by INTRC
(31.25 kHz).
4. OST enabled to count 1024 clock cycles.
5. OST timed out, wait for falling edge of INTRC.
6. OSTS is set.
If the primary oscillator is configured to be anything
other than XT, LP, or HS, then Two-Speed Start-up
mode is disabled, because the primary oscillator will
not require any time to become stable after POR, or an
exit from SLEEP.
7. System clock held low for eight falling edges of
new clock (LP, XT, or HS).
If the IRCF bits of the OSCCON register are configured
to a non-zero value prior to entering SLEEP mode, the
system clock frequency will come from the output of
the INTOSC. The IOFS bit in the OSCCON register will
be clear until the INTOSC is stable. This will allow the
user to determine when the internal oscillator can be
used for time critical applications.
8. System clock is switched to primary source (LP,
XT, or HS).
The software may read the OSTS bit to determine
when the switch over takes place so that any software
timing edges can be adjusted.
FIGURE 15-9:
TWO-SPEED START-UP MODE
CPU Start-up
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2
Q4
Q1
INTRC
OSC1
TOST
OSC2
System Clock
SLEEP
OSTS
Program
Counter
0001h
0003h
PC
0000h
0004h
0005h
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 143
MICROCHIP [ MICROCHIP ]
