PIC16F87/88
TABLE 15-5: PRESCALER/POSTSCALER BIT STATUS
Conditions
Prescaler
Postscaler (PSA = 1)
WDTEN = 0
CLRWDTcommand
Cleared
Cleared
Oscillator fail detected
Exit SLEEP + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit SLEEP + System Clock = XT, HS, LP
Cleared at end of OST Cleared at end of OST
REGISTER 15-3: WDTCON REGISTER (ADDRESS 105h)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
SWDTEN(1)
bit 0
WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’
WDTPS<3:0>: Watchdog Timer Period Select bits
Bit
Value
Prescale
Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16394
1010 = 1:32768
1011 = 1:65536
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit(1)
1= WDT is turned on
0= WDT is turned off
Note 1: If WDTEN configuration bit = 1, then WDT is always enabled, irrespective of this con-
trol bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with this
control bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
TABLE 15-6: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
81h,181h OPTION
RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
2007h
105h
Configuration bits
WDTCON
LVP
—
BOREN MVCLRE FOSC2 PWRTEN WDTEN
FOSC1
FOSC0
—
—
WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 15-1 for operation of these bits.
DS30487B-page 142
Preliminary
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
