PIC16F87/88
FIGURE 11-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RB2/SDO/RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RB5/SS/TX/CK
pin
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRG = 0.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).
11.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB5/SS/TX/CK pin (instead of being supplied inter-
nally in Master mode). This allows the device to trans-
fer or receive data while in SLEEP mode. Slave mode
is entered by clearing bit CSRC (TXSTA<7>).
When setting up a synchronous slave transmission,
follow these steps:
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
11.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
2. Clear bits CREN and SREN.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP mode.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
5. Enable the transmission by setting enable bit
TXEN.
a) The first word will immediately transfer to the
TSR register and transmit.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
b) Thesecondword willremainintheTXREGregister.
c) Flag bit TXIF will not be set.
7. Start transmission by loading data to the TXREG
register.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
RESETS
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x 0000 000u
0Ch
PIR1
—
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
18h
RCSTA
SPEN
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
19h
TXREG USART Transmit Register
0000 0000 0000 0000
8Ch
PIE1
—
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
98h
TXSTA
CSRC
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend:
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 111
MICROCHIP [ MICROCHIP ]
