PIC16F785
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC16F785 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space. Only
the first 2k x 14 (0000h-07FFh) for the PIC16F785 is
physically implemented. Accessing a location above
these boundaries will cause a wrap around within the
first 2k x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F785
PC<12:0>
The data memory (see Figure 2-2) is partitioned into
four banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General
Purpose Registers, implemented as static RAM. The
last sixteen register locations in Bank 1 (F0h-FFh),
Bank 2 (170h-17Fh), and Bank 3 (1F0h-1FFh) point to
addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read.
Seven address bits are required to access any location
in a data memory bank. Two additional bits are required
to access the four banks. When data memory is
accessed directly, the seven Least Significant address
bits are contained within the opcode and the two Most
Significant bits are contained in the STATUS register.
RP0 and RP1 (STATUS<5> and STATUS<6>) are the
two Most Significant data memory address bits and are
also known as the bank select bits. Table 2-1 lists how
to access the four banks of registers.
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
000H
TABLE 2-1:
Bank0
Bank1
Bank2
Bank3
BANK SELECTION
RP1
0
0
1
1
RP0
0
1
0
1
Interrupt Vector
0004
0005
On-chip Program
Memory
07FFH
0800H
2.2.1
GENERAL PURPOSE REGISTER
FILE
1FFFH
The register file banks are organized as 128 x 8 in the
PIC16F785. Each register is accessed, either directly, by
seven address bits within the opcode, or indirectly,
through the File Select Register (FSR). When the FSR is
used to access data memory, the eight Least Significant
data memory address bits are contained in the FSR and
the ninth Most Significant address bit is contained in the
IRP bit (STATUS<7>) of the STATUS register. (see
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-2). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
©
2005 Microchip Technology Inc.
Preliminary
DS41249B-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
