PIC16F785
TABLE 2-3:
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on:
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 22,114
1111 1111 16,114
0000 0000 21,114
0001 1xxx 15,114
xxxx xxxx 22,114
--11 1111 36,114
1111 ---- 42,114
1111 1111 45,114
OPTION_REG
PCL
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
TRISA
TRISB
TRISC
—
—
—
TRISA5
TRISB5
TRISC5
TRISA4
TRISB4
TRISC4
TRISA3
—
TRISA2
—
TRISA1
—
TRISA0
—
TRISB7
TRISC7
TRISB6
TRISC6
TRISC3
TRISC2
TRISC1
TRISC0
Unimplemented
Unimplemented
—
—
—
—
—
—
PCLATH
INTCON
PIE1
—
—
Write Buffer for Upper 5 bits of Program Counter
---0 0000 21,114
0000 0000 17,114
GIE
PEIE
ADIE
T0IE
INTE
C2IE
RAIE
C1IE
T0IF
INTF
RAIF
EEIE
CCP1IE
OSFIE
TMR2IE
TMR1IE 0000 0000 18,114
—
Unimplemented
—
—
—
PCON
OSCCON
OSCTUNE
ANSEL0
PR2
—
—
IRCF1
—
SBOREN
IRCF0
TUN4
—
—
POR
LTS
BOR
SCS
---1 --qq 20,114
-110 q000 33,114
---0 0000 28,114
1111 1111 82,114
1111 1111 55,114
---- 1111 82,115
—
—
IRCF2
—
OSTS(1)
TUN3
ANS3
HTS
TUN2
ANS2
TUN1
ANS1
TUN0
ANS0
ANS7
ANS6
ANS5
ANS4
Timer2 Module Period Register
ANSEL1
—
—
—
—
—
ANS11
ANS10
ANS9
ANS8
Unimplemented
—
—
WPUA
IOCA
—
—
—
WPUA5
IOCA5
WPUA4 WPUA3(2)
WPUA2
IOCA2
WPUA1
IOCA1
WPUA0
IOCA0
--11 1111 36,115
--00 0000 37,115
—
IOCA4
IOCA3
—
Unimplemented
—
—
—
REFCON
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
—
BGST
VRR
VRBB
—
VREN
VR3
VROE
VR2
CVROE
VR1
—
--00 000- 73,115
000- 0000 72,115
C1VREN
EEDAT7
EEADR7
—
C2VREN
EEDAT6
EEADR6
—
VR0
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEADR2
WREN
EEDAT1
EEADR1
WR
EEDAT0 0000 0000 103,115
EEADR0 0000 0000 103,115
EEADR5 EEADR4 EEADR3
WRERR
—
—
RD
---- x000 104,115
---- ---- 104,115
xxxx xxxx 80,115
-000 ---- 84,115
EEPROM Control Register 2 (not a physical register)
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result
ADCS2 ADCS1 ADCS0
—
—
—
—
—
Legend:
Note 1:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this
bit resets to ‘1’.
2:
RA3 pull-up is enabled when MCLRE is ‘1’ in Configuration Word.
DS41249B-page 12
Preliminary
© 2005 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
